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DRAC

Design of accelerators based on RISC technology for the next generation of computers (DRAC).

The accelerators are based on RISC-V technology, an open-source Instruction Set Architecture (ISA) defined by the RISC-V Foundation.

More than 100 institutions worldwide (universities, research centers, companies, etc.) currently support the development of this technology.

The DRAC alliance will create accelerators applied to emerging sectors such as security, personalized medicine (through genomics), or autonomous driving.

Coordinating Entity:

Barcelona Supercomputing Center

The action is articulated in six projects:

  1. Design and implementation of an out-of-order processor. Design, coding, and verification of the processor that will be the core of the alliance's action and onto which various accelerators will be added.
  2. Post-quantum security and virtualization techniques. Many of the current cryptosystems (computer security) will be threatened by the power of quantum computing. Researchers will analyze new cryptographic schemes and design one for the project's processor.
  3. Computer architectures to accelerate genomic analysis applications. Design of new architectures for large-scale genomic data analysis, with significant applications in personalized medicine.
  4. Acceleration of automotive applications with approximate computing in FDSOI technology. Use of approximate computing (hardware that does not always respond with one hundred percent accuracy but reduces energy consumption) for a better performance-energy consumption balance in autonomous driving vehicles.
  5. Integration, layout, and prototyping manufacturing and testing platform. Integration of the various blocks to develop the RISC-V processor and designed accelerators, as well as a testing platform to ensure the processor functions correctly.
  6. Dissemination and technology transfer. Communication of project results and exploitation of the patent through licensing contracts.

 

The UPC research team participating in this project belongs to the departments of Electronic Engineering and Computer Architecture, under the responsibility of Miquel Moreto.

  • High-Performance Integrated Circuits and Systems Group (HIPICS)
  • High-Performance Computing Group (CAP)
  • Virtualization and Operating Systems (VIRTUOS)


This project is co-financed by the European Regional Development Fund of the European Union within the framework of the FEDER Operational Program of Catalonia 2014-2020 with a grant of €2,000,000.00.